1. Field of the Invention
The present invention relates in general to a dual phase locked loop for locking, transmitting and receiving frequencies respectively to selected channel frequencies, and more particularly to a lock apparatus for a dual phase locked loop which is capable of detecting a locked state of the receiving frequency as well as a locked state of the transmitting frequency.
2. Description of the Prior Art
Generally, a phase locked loop, referred to hereinafter as a PLL, has been provided to lock transmitting and receiving frequencies respectively to selected channel frequencies. Early in the PLL, there has individually been provided transmitting and receiving PLLs which lock the transmitting and receiving frequencies, respectively. Progressively, a single PLL has recently been proposed to lock the transmitting and receiving frequencies with a single construction. This single PLL is called a dual PLL. The dual PLL has mostly been employed in such an equipment that has a plurality of transmitting and receiving channels and performs transmission and reception simultaneously at respective selected channel frequencies. Commonly, a radio telephone set is such an equipment.
The conventional dual PLL comprises lock apparatus for dividing transmitting and receiving frequencies according to selected channel frequencies, detecting phase differences between the divided frequencies and a reference frequency, generating, transmitting and receiving phase data based on the detected phase differences and detecting a locked state of the transmitting frequency, loop filters for filtering respectively the transmitting and receiving phase data from the lock apparatus, and voltage controlled oscillators for feeding back respectively oscillating frequencies controlled by the outputs from the loop filters, as the transmitting and receiving frequencies to the lock apparatus and outputting the locked transmitting and receiving frequencies externally, respectively.
Referring to FIG. 1, there is shown an example of the conventional lock apparatus of the dual PLL as mentioned above, in block form. As shown in this figure, the lock apparatus comprises a decoder 8 for decoding channel select data DATA inputted externally thereto synchronously with a clock pulse CLK, a transmitting and receiving channel data ROM 2 for selecting transmitting and receiving channels in accordance with the output data from the decoder 8, a receiving frequency counter 1 for counting a receiving frequency inputted through an input terminal INPUT1 according to the receiving channel data outputted from the transmitting and receiving channel data ROM 2, a transmitting frequency counter 3 for counting a transmitting frequency inputted through another input terminal INPUT2 according to the transmitting channel data outputted from the transmitting and receiving channel data ROM 2, a reference frequency counter 4 for counting an oscillating frequency from an external oscillator OSC and outputting the resulting reference frequency, a receiving phase difference detector 5 for comparing the counted receiving frequency from the receiving frequency counter 1 with the reference frequency from the reference frequency counter 4 to detect a phase difference therebetween and outputting phase data PD1 based on the detected phase difference, a transmitting phase difference detector 7 for comparing the counted transmitting frequency from the transmitting frequency counter 3 with the reference frequency from the reference frequency counter 4 to detect a phase difference therebetween and outputting phase data PD2 based on the detected phase difference, and a transmit lock detector 6 for checking another phase data from the transmitting phase difference detector 7 to detect phase locked state of the transmitting frequency to the reference frequency and outputting lock data LD1 externally in accordance with the detected phase locked state.
The operation of the conventional dual PLL lock apparatus with the above-mentioned construction will now be described.
First, upon receiving an external enable signal ENABLE operating the PLL, the decoder 8 decodes the inputted channel select data DATA synchronously with the clock signal CLK and applies the decoded data to the transmitting and receiving channel data ROM 2. In the transmitting and receiving channel data ROM 2, the transmitting and receiving channel data are generated corresponding to the decoded data from the decoder 8. The generated transmitting and receiving channel data are then applied respectively to the transmitting and receiving frequency counters 3 and 1. In the transmitting and receiving frequency counters 3 and 1, count values are determined respectively based on the applied transmitting and receiving channel data. These count values are determined such that the inputted transmitting and receiving frequencies are divided respectively to be equal to the reference frequency, in the transmitting and receiving frequency counters 3 and 1.
At this time, a transmitting frequency is applied through the input terminal INPUT2 to the transmitting frequency counter 3 and a receiving frequency is applied through the input terminal INPUT1 to the receiving frequency counter 1. The applied transmitting and receiving frequencies are counted based on the respective count values in the transmitting and receiving frequency counters 3 and 1, which then feed the counted transmitting and receiving frequencies respectively to the transmitting and receiving phase difference detectors 7 and 5. At this time, the oscillating frequency from the external oscillator OSC is applied to the reference frequency counter 4, which counts the applied oscillating frequency and outputs the resulting reference frequency to the transmitting and receiving phase difference detectors 7 and 5.
In the transmitting and receiving phase difference detectors 7 and 5, the counted transmitting and receiving frequencies from the transmitting and receiving frequency counters 3 and 1 are compared with the reference frequency from the reference frequency counter 4 and respective phase differences are detected according to the compared results. From the transmitting and receiving phase difference detectors 7 and 5, the transmitting and receiving phase data PD2 and PD1 based on the respective detected phase differences are outputted at a tri-state including high, low and floating states. Also, the transmitting phase difference detector 7 outputs a high or low locked state signal at its separate output terminal to the transmit lock detector 6. In accordance with the high or low locked state signal from the transmitting phase difference detector 7, the transmit lock detector 6 detects the locked state of the transmitting frequency.
Namely, if the phases of the counted transmitting and receiving frequencies from the transmitting and receiving frequency counters 3 and 1 are detected as being equal respectively to the phase of the reference frequency from the reference frequency counter 4 as a result of comparison of the counted transmitting and receiving frequencies with the reference frequency in the transmitting and receiving phase difference detectors 7 and 5, the transmitting and receiving phase data PD2 and PD1 are outputted at high impedance states, respectively, from the transmitting and receiving phase difference detectors 7 and 5. The high or low locked state signal is also outputted at the separate output terminal of the transmitting phase difference detector 7 to the transmit lock detector 6. The transmit lock detector 6 checks the locked state of the transmitting phase difference detector 7 on the basis of the high or low locked state signal. If locked state, the transmit lock detector 6 outputs the lock data LD1 of high impedance externally output of the PLL to notify that the transmitting frequency has been locked.
On the other hand, the transmitting and receiving phase data PD2 and PD1 are applied through corresponding loop filters (not shown) to corresponding voltage controlled oscillators (not shown), which then feed back respectively oscillating frequencies controlled based on the transmitting and receiving phase data PD2 and PD1, as the transmitting and receiving frequencies to the input terminals INPUT2 and INPUT1. The operation, hereinbefore described, is repeatedly performed in this manner.
In the outside of the PLL, a system control unit such as a microcomputer receives the transmit lock data LD1 from the transmit lock detector 6 and recognizes, from the received transmit lock data LD1, that the transmitting frequency has been locked. If recognized, the system control unit performs the accompanying communication control and stops the operation of the PLL lock apparatus for preventing power consumption. Thereafter, upon channel change or power on/off, the system control unit makes the PLL enable, so as to lock the transmitting and receiving frequencies in the above-mentioned manner.
However, the convention lock apparatus for the PLL has a disadvantage, in that it is constructed only to detect the locked state of the transmitting frequency. That is, since only the locked state of the transmitting frequency is detected, the locked state of the receiving frequency is determined at a guess on the basis of the point of time at which the transmitting frequency is locked. For this reason, it takes very long time to lock the receiving frequency. This acts as a delay element on a system requiring a fast response.